ANALYSIS AND DESIGN OF ANALOG INTEGRATED CIRCUITS FIFTH EDITIONPDF|Epub|txt|kindle电子书版本下载

ANALYSIS AND DESIGN OF ANALOG INTEGRATED CIRCUITS FIFTH EDITIONPDF格式电子书版下载

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CHAPTER 1 Models for Integrated-Circuit Active Devices1

1.1 Introduction1

1.2 Depletion Region of a pn Junction1

1.2.1 Depletion-Region Capacitance5

1.2.2 Junction Breakdown6

1.3 Large-Signal Behavior of Bipolar Transistors8

1.3.1 Large-Signal Models in the Forward-Active Region8

1.3.2 Effects of Collector Voltage on Large-Signal Characteristics in the Forward-Active Region14

1.3.3 Saturation and Inverse-Active Regions16

1.3.4 Transistor Breakdown Voltages20

1.3.5 Dependence of Transistor Current Gain βF on Operating Conditions23

1.4 Small-Signal Models of Bipolar Transistors25

1.4.1 Transconductance26

1.4.2 Base-Charging Capacitance27

1.4.3 Input Resistance28

1.4.4 Output Resistance29

1.4.5 Basic Small-Signal Model of the Bipolar Transistor30

1.4.6 Collector-Base Resistance30

1.4.7 Parasitic Elements in the Small-Signal Model31

1.4.8 Specification of Transistor Frequency Response34

1.5 Large-Signal Behavior of Metal-Oxide-Semiconductor Field-Effect Transistors38

1.5.1 Transfer Characteristics of MOS Devices38

1.5.2 Comparison of Operating Regions of Bipolar and MOS Transistors45

1.5.3 Decomposition of Gate-Source Voltage47

1.5.4 Threshold Temperature Dependence47

1.5.5 MOS Device Voltage Limitations48

1.6 Small-Signal Models of MOS Transistors49

1.6.1 Transconductance50

1.6.2 Intrinsic Gate-Source and Gate-Drain Capacitance51

1.6.3 Input Resistance52

1.6.4 Output Resistance52

1.6.5 Basic Small-Signal Model of the MOS Transistor52

1.6.6 Body Transconductance53

1.6.7 Parasitic Elements in the Small-Signal Model54

1.6.8 MOS Transistor Frequency Response55

1.7 Short-Channel Effects in MOS Transistors59

1.7.1 Velocity Saturation from the Horizontal Field59

1.7.2 Transconductance and Transition Frequency63

1.7.3 Mobility Degradation from the Vertical Field65

1.8 Weak Inversion in MOS Transistors65

1.8.1 Drain Current in Weak Inversion66

1.8.2 Transconductance and Transition Frequency in Weak Inversion69

1.9 Substrate Current Flow in MOS Transistors71

A.1.1 Summary of Active-Device Parameters73

CHAPTER 2 Bipolar， MOS， and BiCMOS Integrated-Circuit Technology78

2.1 Introduction78

2.2 Basic Processes in Integrated-Circuit Fabrication79

2.2.1 Electrical Resistivity of Silicon79

2.2.2 Solid-State Diffusion80

2.2.3 Electrical Properties of Diffused Layers82

2.2.4 Photolithography84

2.2.5 Epitaxial Growth86

2.2.6 Ion Implantation87

2.2.7 Local Oxidation87

2.2.8 Polysilicon Deposition87

2.3 High-Voltage Bipolar Integrated-Circuit Fabrication88

2.4 Advanced Bipolar Integrated-Circuit Fabrication92

2.5 Active Devices in Bipolar Analog Integrated Circuits95

2.5.1 Integrated-Circuit npn Transistors96

2.5.2 Integrated-Circuit pnp Transistors107

2.6 Passive Components in Bipolar Integrated Circuits115

2.6.1 Diffused Resistors115

2.6.2 Epitaxial and Epitaxial Pinch Resistors119

2.6.3 Integrated-Circuit Capacitors120

2.6.4 Zener Diodes121

2.6.5 Junction Diodes122

2.7 Modifications to the Basic Bipolar Process123

2.7.1 Dielectric Isolation123

2.7.2 Compatible Processing for High-Performance Active Devices124

2.7.3 High-Performance Passive Components127

2.8 MOS Integrated-Circuit Fabrication127

2.9 Active Devices in MOS Integrated Circuits131

2.9.1 n-Channel Transistors131

2.9.2 p-Channel Transistors144

2.9.3 Depletion Devices144

2.9.4 Bipolar Transistors145

2.10 Passive Components in MOS Technology146

2.10.1 Resistors146

2.10.2 Capacitors in MOS Technology148

2.10.3 Latchup in CMOS Technology151

2.11 BiCMOS Technology152

2.12 Heterojunction Bipolar Transistors153

2.13 Interconnect Delay156

2.14 Economics of Integrated-Circuit Fabrication156

2.14.1 Yield Considerations in Integrated-Circuit Fabrication157

2.14.2 Cost Considerations in Integrated-Circuit Fabrication159

A.2.1 SPICE Model-Parameter Files162

CHAPTER 3 Single-Transistor and Multiple-Transistor Amplifiers169

3.1 Device Model Selection for Approximate Analysis of Analog Circuits170

3.2 Two-Port Modeling of Amplifiers171

3.3 Basic Single-Transistor Amplifier Stages173

3.3.1 Common-Emitter Configuration174

3.3.2 Common-Source Configuration178

3.3.3 Common-Base Configuration182

3.3.4 Common-Gate Configuration185

3.3.5 Common-Base and Common-Gate Configurations with Finite r0187

3.3.5.1 Common-Base and Common-Gate Input Resistance187

3.3.5.2 Common-Base and Common-Gate Output Resistance189

3.3.6 Common-Collector Configuration （Emitter Follower）191

3.3.7 Common-Drain Configuration（Source Follower）194

3.3.8 Common-Emitter Amplifier with Emitter Degeneration196

3.3.9 Common-Source Amplifier with Source Degeneration199

3.4 Multiple-Transistor Amplifier Stages201

3.4.1 The CC-CE， CC-CC， and Darlington Configurations201

3.4.2 The Cascode Configuration205

3.4.2.1 The Bipolar Cascode205

3.4.2.2 The MOS Cascode207

3.4.3 The Active Cascode210

3.4.4 The Super Source Follower212

3.5 Differential Pairs214

3.5.1 The dc Transfer Characteristic of an Emitter-Coupled Pair214

3.5.2 The dc Transfer Characteristic with Emitter Degeneration216

3.5.3 The dc Transfer Characteristic of a Source-Coupled Pair217

3.5.4 Introduction to the Small-Signal Analysis of Differential Amplifiers220

3.5.5 Small-Signal Characteristics of Balanced Differential Amplifiers223

3.5.6 Device Mismatch Effects in Differential Amplifiers229

3.5.6.1 Input Offset Voltage and Current230

3.5.6.2 Input Offset Voltage of the Emitter-Coupled Pair230

3.5.6.3 Offset Voltage of the Emitter-Coupled Pair：Approximate Analysis231

3.5.6.4 Offset Voltage Drift in the Emitter-Coupled Pair233

3.5.6.5 Input Offset Current of the Emitter-Coupled Pair233

3.5.6.6 Input Offset Voltage of the Source-Coupled Pair234

3.5.6.7 Offset Voltage of the Source-Coupled Pair： Approximate Analysis235

3.5.6.8 Offset Voltage Drift in the Source-Coupled Pair236

3.5.6.9 Small-Signal Characteristics of Unbalanced Differential Amplifiers237

A.3.1 Elementary Statistics and the Gaussian Distribution244

CHAPTER 4 Current Mirrors， Active Loads， and References251

4.1 Introduction251

4.2 Current Mirrors251

4.2.1 General Properties251

4.2.2 Simple Current Mirror253

4.2.2.1 Bipolar253

4.2.2.2 MOS255

4.2.3 Simple Current Mirror with Beta Helper258

4.2.3.1 Bipolar258

4.2.3.2 MOS260

4.2.4 Simple Current Mirror with Degeneration260

4.2.4.1 Bipolar260

4.2.4.2 MOS261

4.2.5 Cascode Current Mirror261

4.2.5.1 Bipolar261

4.2.5.2 MOS264

4.2.6 Wilson Current Mirror272

4.2.6.1 Bipolar272

4.2.6.2 MOS275

4.3 Active Loads276

4.3.1 Motivation276

4.3.2 Common-Emitter-Common-Source Amplifier with Complementary Load277

4.3.3 Common-Emitter-Common-Source Amplifier with Depletion Load280

4.3.4 Common-Emitter-Common-Source Amplifier with Diode-Connected Load282

4.3.5 Differential Pair with Current-Mirror Load285

4.3.5.1 Large-Signal Analysis285

4.3.5.2 Small-Signal Analysis286

4.3.5.3 Common-Mode Rejection Ratio291

4.4 Voltage and Current References297

4.4.1 Low-Current Biasing297

4.4.1.1 Bipolar Widlar Current Source297

4.4.1.2 MOS Widlar Current Source300

4.4.1.3 Bipolar Peaking Current Source301

4.4.1.4 MOS Peaking Current Source302

4.4.2 Supply-Insensitive Biasing303

4.4.2.1 Widlar Current Sources304

4.4.2.2 Current Sources Using Other Voltage Standards305

4.4.2.3 Self-Biasing307

4.4.3 Temperature-Insensitive Biasing315

4.4.3.1 Band-Gap-Referenced Bias Circuits in Bipolar Technology315

4.4.3.2 Band-Gap-Referenced Bias Circuits in CMOS Technology321

A.4.1 Matching Considerations in Current Mirrors325

A.4.1.1 Bipolar325

A.4.1.2 MOS328

A.4.2 Input Offset Voltage of Differential Pair with Active Load330

A.4.2.1 Bipolar330

A.4.2.2 MOS332

CHAPTER 5 Output Stages341

5.1 Introduction341

5.2 The Emitter Follower as an Output Stage341

5.2.1 Transfer Characteristics of the Emitter-Follower341

5.2.2 Power Output and Efficiency344

5.2.3 Emitter-Follower Drive Requirements351

5.2.4 Small-Signal Properties of the Emitter Follower352

5.3 The Source Follower as an Output Stage353

5.3.1 Transfer Characteristics of the Source Follower353

5.3.2 Distortion in the Source Follower355

5.4 Class B Push-Pull Output Stage359

5.4.1 Transfer Characteristic of the Class B Stage360

5.4.2 Power Output and Efficiency of the Class B Stage362

5.4.3 Practical Realizations of Class B Complementary Output Stages366

5.4.4 All-npn Class B Output Stage373

5.4.5 Quasi-Complementary Output Stages376

5.4.6 Overload Protection377

5.5 CMOS Class AB Output Stages379

5.5.1 Common-Drain Configuration380

5.5.2 Common-Source Configuration with Error Amplifiers381

5.5.3 Alternative Configurations388

5.5.3.1 Combined Common-Drain Common-Source Configuration388

5.5.3.2 Combined Common-Drain Common-Source Configuration with High Swing390

5.5.3.3 Parallel Common-Source Configuration390

CHAPTER 6 Operational Amplifiers with Single-Ended Outputs400

6.1 Applications of Operational Amplifiers401

6.1.1 Basic Feedback Concepts401

6.1.2 Inverting Amplifier402

6.1.3 Noninverting Amplifier404

6.1.4 Differential Amplifier404

6.1.5 Nonlinear Analog Operations405

6.1.6 Integrator， Differentiator406

6.1.7 Internal Amplifiers407

6.1.7.1 Switched-Capacitor Amplifier407

6.1.7.2 Switched-Capacitor Integrator412

6.2 Deviations from Ideality in Real Operational Amplifiers415

6.2.1 Input Bias Current415

6.2.2 Input Offset Current416

6.2.3 Input Offset Voltage416

6.2.4 Common-Mode Input Range416

6.2.5 Common-Mode Rejection Ratio （CMRR）417

6.2.6 Power-Supply Rejection Ratio （PSRR）418

6.2.7 Input Resistance420

6.2.8 Output Resistance420

6.2.9 Frequency Response420

6.2.10 Operational-Amplifier Equivalent Circuit420

6.3 Basic Two-Stage MOS Operational Amplifiers421

6.3.1 Input Resistance， Output Resistance，and Open-Circuit Voltage Gain422

6.3.2 Output Swing423

6.3.3 Input Offset Voltage424

6.3.4 Common-Mode Rejection Ratio427

6.3.5 Common-Mode Input Range427

6.3.6 Power-Supply Rejection Ratio（PSRR）430

6.3.7 Effect of Overdrive Voltages434

6.3.8 Layout Considerations435

6.4 Two-Stage MOS Operational Amplifiers with Cascodes438

6.5 MOS Telescopic-Cascode Operational Amplifiers439

6.6 MOS Folded-Cascode Operational Amplifiers442

6.7 MOS Active-Cascode Operational Amplifiers446

6.8 Bipolar Operational Amplifiers448

6.8.1 The dc Analysis of the NE5234 Operational Amplifier452

6.8.2 Transistors that Are Normally Off467

6.8.3 Small-Signal Analysis of the NE5234 Operational Amplifier469

6.8.4 Calculation of the Input Offset Voltage and Current of the NE5234477

CHAPTER 7 Frequency Response of Integrated Circuits490

7.1 Introduction490

7.2 Single-Stage Amplifiers490

7.2.1 Single-Stage Voltage Amplifiers and the Miller Effect490

7.2.1.1 The Bipolar Differential Amplifier： Differential-Mode Gain495

7.2.1.2 The MOS Differential Amplifier： Differential-Mode Gain499

7.2.2 Frequency Response of the Common-Mode Gain for a Differential Amplifier501

7.2.3 Frequency Response of Voltage Buffers503

7.2.3.1 Frequency Response of the Emitter Follower505

7.2.3.2 Frequency Response of the Source Follower511

7.2.4 Frequency Response of Current Buffers514

7.2.4.1 Common-Base Amplifier Frequency Response516

7.2.4.2 Common-Gate Amplifier Frequency Response517

7.3 Multistage Amplifier Frequency Response518

7.3.1 Dominant-Pole Approximation518

7.3.2 Zero-Value Time Constant Analysis519

7.3.3 Cascode Voltage-Amplifier Frequency Response524

7.3.4 Cascode Frequency Response527

7.3.5 Frequency Response of a Current Mirror Loading a Differential Pair534

7.3.6 Short-Circuit Time Constants536

7.4 Analysis of the Frequency Response of the NE5234 Op Amp539

7.4.1 High-Frequency Equivalent Circuit of the NE5234539

7.4.2 Calculation of the -3-dB Frequency of the NE5234540

7.4.3 Nondominant Poles of the NE5234542

7.5 Relation Between Frequency Response and Time Response542

CHAPTER 8 Feedback553

8.1 Ideal Feedback Equation553

8.2 Gain Sensitivity555

8.3 Effect of Negative Feedback on Distortion555

8.4 Feedback Configurations557

8.4.1 Series-Shunt Feedback557

8.4.2 Shunt-Shunt Feedback560

8.4.3 Shunt-Series Feedback561

8.4.4 Series-Series Feedback562

8.5 Practical Configurations and the Effect of Loading563

8.5.1 Shunt-Shunt Feedback563

8.5.2 Series-Series Feedback569

8.5.3 Series-Shunt Feedback579

8.5.4 Shunt-Series Feedback583

8.5.5 Summary587

8.6 Single-Stage Feedback587

8.6.1 Local Series-Series Feedback587

8.6.2 Local Series-Shunt Feedback591

8.7 The Voltage Regulator as a Feedback Circuit593

8.8 Feedback Circuit Analysis Using Return Ratio599

8.8.1 Closed-Loop Gain Using Return Ratio601

8.8.2 Closed-Loop Impedance Formula Using Return Ratio607

8.8.3 Summary—Return-Ratio Analysis612

8.9 Modeling Input and Output Ports in Feedback Circuits613

CHAPTER 9 Frequency Response and Stability of Feedback Amplifiers624

9.1 Introduction624

9.2 Relation Between Gain and Bandwidth in Feedback Amplifiers624

9.3 Instability and the Nyquist Criterion626

9.4 Compensation633

9.4.1 Theory of Compensation633

9.4.2 Methods of Compensation637

9.4.3 Two-Stage MOS Amplifier Compensation643

9.4.4 Compensation of Single-Stage CMOS Op Amps650

9.4.5 Nested Miller Compensation654

9.5 Root-Locus Techniques664

9.5.1 Root Locus for a Three-Pole Transfer Function665

9.5.2 Rules for Root-Locus Construction667

9.5.3 Root Locus for Dominant-Pole Compensation676

9.5.4 Root Locus for Feedback-Zero Compensation677

9.6 Slew Rate681

9.6.1 Origin of Slew-Rate Limitations681

9.6.2 Methods of Improving Slew-Rate in Two-Stage Op Amps685

9.6.3 Improving Slew-Rate in Bipolar Op Amps687

9.6.4 Improving Slew-Rate in MOS Op Amps688

9.6.5 Effect of Slew-Rate Limitations on Large-Signal Sinusoidal Performance692

A.9.1 Analysis in Terms of Return-Ratio Parameters693

A.9.2 Roots of a Quadratic Equation694

CHAPTER 10 Nonlinear Analog Circuits704

10.1 Introduction704

10.2 Analog Multipliers Employing the Bipolar Transistor704

10.2.1 The Emitter-Coupled Pair as a Simple Multiplier704

10.2.2 The dc Analysis of the Gilbert Multiplier Cell706

10.2.3 The Gilbert Cell as an Analog Multiplier708

10.2.4 A Complete Analog Multiplier711

10.2.5 The Gilbert Multiplier Cell as a Balanced Modulator and Phase Detector712

10.3 Phase-Locked Loops （PLL）716

10.3.1 Phase-Locked Loop Concepts716

10.3.2 The Phase-Locked Loop in the Locked Condition718

10.3.3 Integrated-Circuit Phase-Locked Loops727

10.4 Nonlinear Function Synthesis731

CHAPTER 11 Noise in Integrated Circuits736

11.1 Introduction736

11.2 Sources of Noise736

11.2.1 Shot Noise736

11.2.2 Thermal Noise740

11.2.3 Flicker Noise （1 / f Noise）741

11.2.4 Burst Noise （Popcorn Noise）742

11.2.5 Avalanche Noise743

11.3 Noise Models of Integrated-Circuit Components744

11.3.1 Junction Diode744

11.3.2 Bipolar Transistor745

11.3.3 MOS Transistor746

11.3.4 Resistors747

11.3.5 Capacitors and Inductors747

11.4 Circuit Noise Calculations748

11.4.1 Bipolar Transistor Noise Performance750

11.4.2 Equivalent Input Noise and the Minimum Detectable Signal754

11.5 Equivalent Input Noise Generators756

11.5.1 Bipolar Transistor Noise Generators757

11.5.2 MOS Transistor Noise Generators762

11.6 Effect of Feedback on Noise Performance764

11.6.1 Effect of Ideal Feedback on Noise Performance764

11.6.2 Effect of Practical Feedback on Noise Performance765

11.7 Noise Performance of Other Transistor Configurations771

11.7.1 Common-Base Stage Noise Performance771

11.7.2 Emitter-Follower Noise Performance773

11.7.3 Differential-Pair Noise Performance773

11.8 Noise in Operational Amplifiers776

11.9 Noise Bandwidth782

11.10 Noise Figure and Noise Temperature786

11.10.1 Noise Figure786

11.10.2 Noise Temperature790

CHAPTER 12 Fully Differential Operational Amplifiers796

12.1 Introduction796

12.2 Properties of Fully Differential Amplifiers796

12.3 Small-Signal Models for Balanced Differential Amplifiers799

12.4 Common-Mode Feedback804

12.4.1 Common-Mode Feedback at Low Frequencies805

12.4.2 Stability and Compensation Considerations in a CMFB Loop810

12.5 CMFB Circuits811

12.5.1 CMFB Using Resistive Divider and Amplifier812

12.5.2 CMFB Using Two Differential Pairs816

12.5.3 CMFB Using Transistors in the Triode Region819

12.5.4 Switched-Capacitor CMFB821

12.6 Fully Differential Op Amps823

12.6.1 A Fully Differential Two-Stage Op Amp823

12.6.2 Fully Differential Telescopic Cascode Op Amp833

12.6.3 Fully Differential Folded-Cascode Op Amp834

12.6.4 A Differential Op Amp with Two Differential Input Stages835

12.6.5 Neutralization835

12.7 Unbalanced Fully Differential Circuits838

12.8 Bandwidth of the CMFB Loop844

12.9 Analysis of a CMOS Fully Differential Folded-Cascode Op Amp845

12.9.1 DC Biasing848

12.9.2 Low-Frequency Analysis850

12.9.3 Frequency and Time Responses in a Feedback Application856

Index871