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1 Device Physics1

1.1 Semiconductors1

1.1.1 Generation and Recombination4

1.1.2 Extrinsic Semiconductors6

1.1.3 Diffusion and Drift9

1.2 PN Junctions10

1.2.1 Depletion Regions10

1.2.2 PN Diodes13

1.2.3 Schottky Diodes15

1.2.4 Zener Diodes17

1.2.5 Ohmic Contacts19

1.3 Bipolar Junction Transistors20

1.3.1 Beta22

1.3.2 I-V Characteristics23

1.4 MOS Transistors24

1.4.1 Threshold Voltage27

1.4.2 I-V Characteristics29

1.5 JFET Transistors31

1.6 Summary33

1.7 Exercises34

2 Semiconductor Fabrication36

2.1 Silicon Manufacture36

2.1.1 Crystal Growth37

2.1.2 Wafer Manufacturing38

2.1.3 The Crystal Structure of Silicon38

2.2 Photolithography40

2.2.1 Photoresists40

2.2.2 Photomasks and Reticles41

2.2.3 Patterning42

2.3 Oxide Growth and Removal42

2.3.1 Oxide Growth and Deposition43

2.3.2 Oxide Removal44

2.3.3 Other Effects of Oxide Growth and Removal46

2.3.4 Local Oxidation of Silicon （LOCOS）48

2.4 Diffusion and Ion Implantation49

2.4.1 Diffusion50

2.4.2 Other Effects of Diffusion52

2.4.3 Ion Implantation53

2.5 Silicon Deposition55

2.5.1 Epitaxy56

2.5.2 Polysilicon Deposition58

2.6 Metallization58

2.6.1 Deposition and Removal of Aluminum59

2.6.2 Refractory Barrier Metal60

2.6.3 Silicidation62

2.6.4 Interlevel Oxide，Interlevel Nitride，and Protective Overcoat63

2.7 Assembly64

2.7.1 Mount and Bond66

2.7.2 Packaging69

2.8 Summary69

2.9 Exercises69

3 Representative Processes72

3.1 Standard Bipolar72

3.1.1 Essential Features72

3.1.2 Fabrication Sequence73

Starting Material73

N-Buried Layer73

Epitaxial Growth74

Isolation Diffusion74

Deep-N+74

Base Implant75

Emitter Diffusion75

Contact76

Metallization76

Protective Overcoat77

3.1.3 Available Devices77

NPN Transistors77

PNP Transistors79

Resistors81

Capacitors83

3.1.4 Process Extensions84

Up-down Isolation84

Double-level Metal84

Schottky Diodes85

High-Sheet Resistors86

Super-beta Transistors86

3.2 Polysilicon-Gate CMOS87

3.2.1 Essential Features88

3.2.2 Fabrication Sequence89

Starting Material89

Epitaxial Growth89

N-well Diffusion89

Inverse Moat90

Channel Stop Implants90

LOCOS Processing and Dummy Gate Oxidation91

Threshold Adjust92

Polysilicon Deposition and Patterning93

Source/Drain Implants93

Contacts94

Metallization94

Protective Overcoat94

3.2.3 Available Devices95

NMOS Transistors95

PMOS Transistors97

Substrate PNP Transistors98

Resistors98

Capacitors100

3.2.4 Process Extensions100

Double-level Metal100

Silicidation101

Lightly Doped Drain （LDD） Transistors101

Extended-Drain，High-Voltage Transistors103

3.3 Analog BiCMOS104

3.3.1 Essential Features104

3.3.2 Fabrication Sequence106

Starting Material106

N-buried Layer106

Epitaxial Growth106

N-well DiFFusion and Deep-N+107

Base Implant107

Inverse Moat108

Channel Stop Implants108

LOCOS Processing and Dummy Gate Oxidation108

ThresholdAdjust109

Polysilicon Deposition and Pattern109

Source/Drain Implants109

Metallization and Protective Overcoat110

Process Comparison110

3.3.3 Available Devices111

NPN Transistors112

PNP Transistors112

Resistors115

3.4 Summary115

3.5 Exercises116

4 Failure Mechanisms118

4.1 Electrical Overstress118

4.1.1 Electrostatic Discharge （ESD）118

Effects120

Preventative Measures120

4.1.2 Electromigration121

Effects121

Preventative Measures122

4.1.3 The Antenna Effect122

4.2 Contamination124

4.2.1 D124

Corrosion124

Effects124

Preventative Measures125

4.2.2 Mobile Ion Contamination125

Effects125

Preventative Measures126

4.3 Surface Effects128

4.3.1 Hot Carrier Injection128

Effects128

Preventative Measures130

4.3.2 Parasitic Channels and Charge Spreading131

Effects131

Preventative Measures （Standard Bipolar）133

Preventative Measures （CMOS and BiCMOS）137

4.4 Parasitics139

4.4.1 Substrate Debiasing140

Effects140

Preventative Measures142

4.4.2 Minority-Carrier Injection143

Effects143

Preventative Measures （Substrate Injection）146

Preventative Measures （Cross-injection）151

4.5 Summary153

4.6 Exercises153

5 Resistors156

5.1 Resistivity and Sheet Resistance156

5.2 Resistor Layout158

5.3 Resistor Variability162

5.3.1 Process Variation162

5.3.2 Temperature Variation163

5.3.3 Nonlinearity163

5.3.4 Contact Resistance166

5.4 Resistor Parasitics167

5.5 Comparison of Available Resistors170

5.5.1 Base Resistors170

5.5.2 Emitter Resistors171

5.5.3 Base Pinch Resistors172

5.5.4 High-Sheet Resistors173

5.5.5 Epi Pinch Resistors175

5.5.6 Metal Resistors176

5.5.7 Poly Resistors177

5.5.8 NSD and PSD Resistors180

5.5.9 N-well Resistors180

5.5.10 Thin-film Resistors181

5.6 Adjusting Resistor Values182

5.6.1 Tweaking Resistors182

Sliding Contacts183

Sliding Heads184

Trombone Slides184

Metal Options184

5.6.2 Trimming Resistors185

Fuses185

Zener Zaps189

Laser Trims190

5.7 Summary191

5.8 Exercises192

6 Capacitors194

6.1 Capacitance194

6.2 Capacitor Variability200

6.2.1 Process Variation200

6.2.2 Voltage Modulation and Temperature Variation201

6.3 Capacitor Parasitics203

6.4 Comparison of Available Capacitors205

6.4.1 Base-emitter Junction Capacitors205

6.4.2 MOS Capacitors207

6.4.3 Poly-poly Capacitors209

6.4.4 Miscellaneous Styles of Capacitors211

6.5 Summary212

6.6 Exercises212

7 Matching of Resistors and Capacitors214

7.1 Measuring Mismatch214

7.2 Causes of Mismatch217

7.2.1 Random Statistical Fluctuations217

7.2.2 Process Biases219

7.2.3 Pattern Shift220

7.2.4 Variations in Polysilicon Etch Rate222

7.2.5 Diffusion Interactions224

7.2.6 Stress Gradients and Package Shifts226

Piezoresistivity227

Gradients and Centroids229

Common-centroid Layout231

Location and Orientation235

7.2.7 Temperature Gradients and Thermoelectrics236

Thermal Gradients238

Thermoelectric Effects240

7.2.8 Electrostatic Interactions242

Voltage Modulation242

Charge Spreading245

Dielectric Polarization246

Dielectric Relaxation248

7.3 Rules for Device Matching249

7.3.1 Rules for Resistor Matching249

7.3.2 Rules for Capacitor Matching253

7.4 Summary257

7.5 Exercises257

8 Bipolar Transistors260

8.1 Topics in Bipolar Transistor Operation260

8.1.1 Beta Rolloff262

8.1.2 Avalanche Breakdown262

8.1.3 Thermal Runaway and Secondary Breakdown264

8.1.4 Saturation in NPN Transistors266

8.1.5 Saturation in Lateral PNP Transistors270

8.1.6 Parasitics of Bipolar Transistors272

8.2 Standard Bipolar Small-signal Transistors274

8.2.1 The Standard Bipolar NPN Transistor274

Construction of Small-signal NPN Transistors276

8.2.2 The Standard Bipolar Substrate PNP Transistor279

Construction of Small-signal Substrate PNP Transistors281

8.2.3 The Standard Bipolar Lateral PNP Transistor283

Construction of Small-signal Lateral PNP Transistors285

8.2.4 High-voltage Bipolar Transistors291

8.3.Alternative Small-signal Bipolar Transistors293

8.3.1 Extensions to Standard Bipolar293

8.3.2 Analog BiCMOS Bipolar Transistors294

8.3.3 Bipolar Transistors in a CMOS Process297

8.3.4 Advanced-technology Bipolar Transistors299

8.4 Summary302

8.5 Exercises303

9 Applications of Bipolar Transistors306

9.1 Power Bipolar Transistors306

9.1.1 Failure Mechanisms of NPN Power Trapsistors307

Emitter Debiasing307

Thermal Runaway and Secondary Breakdown309

9.1.2 Layout of Power NPN Transistors311

The Interdigitated-emitter Transistor311

The Wide-emitter Narrow-contact Transistor314

The Christmas-tree Device315

The Cruciform-emitter Transistor316

Power Transistor Layout in Analog BiCMOS317

Selecting a Power Transistor Layout318

9.1.3 Saturation Detection and Limiting319

9.2 Matching Bipolar Transistors322

9.2.1 Random Variations323

9.2.2 Emitter Degeneration325

9.2.3 NBL Shadow327

9.2.4 Thermal Gradients328

9.2.5 Stress Gradients332

9.3 Rules for Bipolar Transistor Matching334

9.3.1 Rules for Matching NPN Transistors335

9.3.2 Rules for Matching Lateral PNP Transistors337

9.4 Summary340

9.5 Exercises340

10 Diodes343

10.1 Diodes in Standard Bipolar343

10.1.1.Diode-connected Transistors343

10.1.2 Zener Diodes346

Surface Zener Diodes347

Buried Zeners349

10.1.3 Schottky Diodes352

10.2 Diodes in CMOS and BiCMOS Processes356

10.3 Matching Diodes359

10.3.1 Matching PN Junction Diodes359

10.3.2 Matching Zener Diodes360

10.3.3 Matching Schottky Diodes361

10.4 Summary362

10.5 Exercises362

11 MOS Transistors364

11.1 Topics in MOS Transistor Operation364

11.1.1 Modeling the MOS Transistor364

Device Transconductance365

Threshold Voltage367

11.1.2 Parasitics of MOS Transistors370

Breakdown Mechanisms372

CMOS Latchup375

11.2 Self-aligned Poly-Gate CMOS Transistors376

11.2.1 Coding the MOS Transistor377

Width and Length378

11.2.2 N-well and P-well Processes379

11.2.3 Channel Stops381

11.2.4 Threshold Adjust Implants383

11.2.5 Scaling the Transistor386

11.2.6 Variant Structures388

Serpentine Transistors391

Annular Transistors391

11.2.7 Backgate Contacts393

11.3 Summary396

11.4 Exercises396

12 Applications of MOS Transistors399

12.1 Extended-voltage Transistors399

12.1.1 LDD and DDD Transistors400

12.1.2 Extended-drain Transistors403

Extended-drain NMOS Transistors403

Extended-drain PMOS Transistors405

12.1.3 Multiple Gate Oxides405

12.2 Power MOS Transistors407

Thermal Runaway407

Secondary Breakdown408

Rapid Transient Overload408

MOS Switches versus Bipolar Switches409

12.2.1 Conventional MOS Power Transistors410

The Rectangular Device411

The Diagonal Device413

Computation of R M413

Other Considerations414

Nonconventional Structures416

12.2.2 DMOS Transistors417

The Lateral DMOS Transistor418

The DMOS NPN420

12.3 The JFET Transistor422

12.3.1 Modeling the JFET422

12.3.2 JFET Layout423

12.4 MOS Transistor Matching426

12.4.1 Geometric Effects427

Gate Area428

Gate Oxide Thickness428

Channel Length Modulation429

Orientation429

12.4.2 Diffusion and Etch Effects430

Polysilicon Etch Rate Variations430

Contacts OverActive Gate431

Diffusions Near the Channel432

PMOS versus NMOS Transistors432

12.4.3 Thermal and Stress Effects433

Oxide Thickness Gradients433

Stress Gradients433

Metallization-induced Stresses434

Thermal Gradients434

12.4.4 Common-centroid Layout of MOS Transistors435

12.5 Rules for MOS Transistor Matching439

12.6 Summary442

12.7 Exercises443

13 Special Topics445

13.1 Merged Devices445

13.1.1 Flawed Device Mergers446

13.1.2 Successful Device Mergers450

13.1.3 Low-risk Merged Devices452

13.1.4 Medium-risk Merged Devices453

13.1.5 Devising New Merged Devices455

13.2 Guard Rings455

13.2.1 Standard Bipolar Electron Guard Rings456

13.2.2 Standard Bipolar Hole Guard Rings457

13.2.3 Guard Rings in CMOS and BiCMOS Designs458

13.3 Single-level Interconnection460

13.3.1 Mock Layouts and Stick Diagrams461

13.3.2 Techniques for Crossing Leads463

13.3.3 Types of Tunnels464

13.4 Constructing the Padring466

13.4.1 Scribe Streets and Alignment Markers466

13.4.2 Bondpads，Trimpads，and Testpads468

13.4.3 ESD Structures471

Zener Clamp473

Two-stage Zener Clamps475

Buffered Zener Clamp476

VcEs Clamp478

VcEs Clamp479

Antiparallel Diode Clamps480

Additional ESD Structures for CMOS Processes480

13.4.4 Selecting ESD Structures483

13.5 Exercises485

14 Assembling the Die488

14.1 Die Planning488

14.1.1 Cell Area Estimation489

Resistors489

Capacitors489

Vertical Bipolar Transistors489

Lateral PNP Transistors490

MOS Transistors490

MOS Power Transistors490

Computing Cell Area491

14.1.2 Die Area Estimation491

14.1.3 Gross Profit Margin494

14.2 Floorplanning495

14.3 Top-level Interconnection500

14.3.1 Principles of Channel Routing501

14.3.2 Special Routing Techniques503

Kelvin Connections503

Noisy Signals and Sensitive Signals504

14.3.3 Electromigration506

14.3.4 Minimizing Stress Effects508

14.4 Conclusion510

14.5 Exercises510

Appendices513

A.Table of Acronyms Used in the Text513

B.The Miller Indices of a Cubic Crystal516

C.Sample Layout Rules519

D.Mathematical Derivations527

E.Sources for Layout Editor Software532

Index533