Computer organization and design the hardware/software interface Fifth Edition Asian Edition = 计算机组成PDF|Epub|txt|kindle电子书版本下载

Computer organization and design the hardware/software interface Fifth Edition Asian Edition = 计算机组成PDF格式电子书版下载

注意：本站所有压缩包均有解压码： 点击下载压缩包解压工具

CHAPTERS2

1Computer Abstractions and Technology2

1.1 Introduction3

1.2 Eight Great Ideas in Computer Architecture11

1.3 Below Your Program13

1.4 Under the Covers16

1.5 Technologies for Building Processors and Memory24

1.6 Performance28

1.7 The Power Wall40

1.8 The Sea Change：The Switch from Uniprocessors to Multiprocessors43

1.9 Real Stuff：Benchmarking the Intel Core i746

1.10 Fallacies and Pitfalls49

1.11 Concluding Remarks52

1.12 Historical Perspective and Further Reading54

1.13 Exercises54

2Instructions：Language of the Computer60

2.1 Introduction62

2.2 Operations of the Computer Hardware63

2.3 Operands of the Computer Hardware66

2.4 Signed and Unsigned Numbers73

2.5 Representing Instructions in the Computer80

2.6 Logical Operations87

2.7 Instructions for Making Decisions90

2.8 Supporting Procedures in Computer Hardware96

2.9 MIPS Addressing for 32-Bit Immediates and Addresses106

2.10 Parallelism and Instructions：Synchronization116

2.11 Translating and Starting a Program118

2.12 A C Sort Example to Put It All Together126

2.13 Advanced Material：Compiling C134

2.14 Real Stuff：ARMv7（32-bit） Instructions134

2.15 Real Stuff：x86 Instructions138

2.16 Real Stuff：ARMv8（64-bit） Instructions147

2.17 Fallacies and Pitfalls148

2.18 Concluding Remarks150

2.19 Historical Perspective and Further Reading152

2.20 Exercises153

3Arithmetic for Computers164

3.1 Introduction166

3.2 Addition and Subtraction166

3.3 Multiplication171

3.4 Division177

3.5 Floating Point184

3.6 Parallelism and Computer Arithmetic：Subword Parallelism210

3.7 Real Stuff：Streaming SIMD Extensions and Advanced Vector Extensions in x86212

3.8 Going Faster：Subword Parallelism and Matrix Multiply213

3.9 Fallacies and Pitfalls217

3.10 Concluding Remarks220

3.11 Historical Perspective and Further Reading224

3.12 Exercises225

4The Processor230

4.1 Introduction232

4.2 Logic Design Conventions236

4.3 Building a Datapath239

4.4 A Simple Implementation Scheme247

4.5 An Overview of Pipelining260

4.6 Pipelined Datapath and Control274

4.7 Data Hazards：Forwarding versus Stalling291

4.8 Control Hazards304

4.9 Exceptions313

4.10 Parallelism via Instructions320

4.11 Real Stuff：The ARM Cortex-A8 and Intel Core i7 Pipelines332

4.12 Going Faster：Instruction-Level Parallelism and Matrix Multiply339

4.13 Advanced Topic：An Introduction to Digital Design Using a Hardware Design Language to Describe and Model a Pipeline and More Pipelining Illustrations342

4.14 Fallacies and Pitfalls343

4.15 Concluding Remarks344

4.16 Historical Perspective and Further Reading345

4.17 Exercises345

5Large and Fast：Exploiting Memory Hierarchy360

5.1 Introduction362

5.2 Memory Technologies366

5.3 The Basics of Caches371

5.4 Measuring and Improving Cache Performance386

5.5 Dependable Memory Hierarchy406

5.6 Virtual Machines412

5.7 Virtual Memory415

5.8 A Common Framework for Memory Hierarchy442

5.9 Using a Finite-State Machine to Control a Simple Cache449

5.10 Parallelism and Memory Hierarchies：Cache Coherence454

5.11 Parallelism and Memory Hierarchy：Redundant Arrays of Inexpensive Disks458

5.12 Advanced Material：Implementing Cache Controllers458

5.13 Real Stuff：The ARM Cortex-A8 and Intel Core i7 MemoryHierarchies459

5.14 Going Faster：Cache Blocking and Matrix Multiply463

5.15 Fallacies and Pitfalls466

5.16 Concluding Remarks470

5.17 Historical Perspective and Further Reading471

5.18 Exercises471

6Parallel Processors from Client to Cloud488

6.1 Introduction490

6.2 The Difficulty of Creating Parallel Processing Programs492

6.3 SISD，MIMD，SIMD，SPMD，and Vector497

6.4 Hardware Multithreading504

6.5 Multicore and Other Shared Memory Multiprocessors507

6.6 Introduction to Graphics Processing Units512

6.7 Clusters，Warehouse Scale Computers，and Other Message-Passing Multiprocessors519

6.8 Introduction to Multiprocessor Network Topologies524

6.9 Communicating to the Outside World：Cluster Networking527

6.10 Multiprocessor Benchmarks and Performance Models528

6.11 Real Stuff：Benchmarking Intel Core i7 versus NVIDIA Tesla GPU538

6.12 Going Faster：Multiple Processors and Matrix Multiply543

6.13 Fallacies and Pitfalls546

6.14 Concluding Remarks548

6.15 Historical Perspective and Further Reading551

6.16 Exercises551

APPENDICES？564

A Assemblers，Linkers，and the SPIM Simulator564

A.1 Introduction565

A.2 Assemblers572

A.3 Linkers580

A.4 Loading581

A.5 Memory Usage582

A.6 Procedure Call Convention584

A.7 Exceptions and Interrupts595

A.8 Input and Output600

A.9 SPIM602

A.10 MIPS R2000 Assembly Language607

A.11 Concluding Remarks643

A.12 Exercises644

B TH-2 High Performance Computing System646

B.1 Introduction647

B.2 Compute Node647

B.3 The Frontend Processors649

B.4 The Interconnect650

B.5 The Software Stack651

B.6 LINPACK Benchmark Run（HPL）651

B.7 Concluding Remarks652

F Networks-on-Chip654

F1 Introduction655

F2 Communication Centric Design655

F3 The Design Space Exploration of NoCs657

F4 Router Micro-architecture660

F5 Performance Metric661

F6 Concluding Remarks661

Index663