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About This Book1

The MindShare Architecture Series1

Cautionary Note2

This Book Assumes PCI Background Knowledge3

Specifications This Book Is Based On3

Organization of This Book3

Who This Book Is For4

Prerequisite Knowledge4

Documentation Conventions5

Hexadecimal Notation5

Binary Notation5

Decimal Notation5

Bits Versus Bytes Notation5

Bit Fields(Logical Groups of Bits or Signals)6

Timing Diagram Drawing Convention6

Clock-by-Clock Timing Diagram Description8

Signal Polarity8

Visit Our Web Site8

We Want Your Feedback9

Part 1：Basic Concepts13

Chapter 1：PCI Needed Improvement13

Wait States Yield Poor Performance13

Relatively Slow Clock Speed14

Transfer Size Unknown14

PCI Delayed Transactions Are Inefficient15

Initiator Retries Use Up Valuable Bus Time15

Initiator Doesn′t Supply Transfer Count15

Delayed Completion16

Initiator′s Transaction ID Is Sketchy at Best16

Snoops Hurt Performance16

Host/PCIX Bridge Knows AGP′s Area of Memory Is Non-Cacheable16

Memory Used by PCI Masters May or May Not Be Cached17

Snoops Slow Down PCI Accesses to Main Memory17

Snoop Traffic on Processor Bus Can Hurt Processor(s)17

Main Memory Less Available to Processor(s)17

Latency Timer Use Not Optimized in PCI19

Min_Gnt Register：Timeslice Request19

Latency Timer：“Timeslice”Register19

Insufficient Info to Select a Good Value20

Data Phase Parity Error Recovery Usually Not Possible21

PCI Data Parity Error Recovery21

Important Note Regarding Chipsets That Monitor PERR22

No Indication of Device Width22

MSI Feature Optional in PCI Environment22

Introduction22

Advantages of MSI Interrupts23

Power Management Optional23

Legacy PCI Devices—No Standard PM Method23

Device Support for PCI PM Optional23

Discovering Function′s PM Capability23

Configuration Software Constrained by 32-Bit Memory BARs26

Stepping Yields Poor Performance27

Chapter 2：PCI-X Improves on PCI29

PCI-X Is Backward-Compatible With PCI29

PCI-X Is More System-Centric Than PCI30

Higher Clock Speeds Possible31

Wait States Eliminated31

Data Transferred in Blocks31

In PCI，Data Transferred as a Series of Data Items31

In PCI-X，Data Transferred as a Series of Blocks32

Master Cannot Delay Transfer of First Data Block32

Target Can Only Delay Transfer of First Block32

Master and Target Can Only Disconnect on Block Boundaries32

But…There Are Two Exceptions32

Disconnecting on Block Boundaries33

Master Disconnection of a Transfer33

Target Disconnection of a Transfer33

Latency Timer Usage33

Requester and Completer34

Transfer Size Specified34

Requester ID and Transaction ID Are Specified34

Split Transactions Replace Delayed Transactions35

Target Cannot Transfer Data Within 16 Clocks From FRAME# Assertion35

Long-Latency Access Handling in PCI35

Long-Latency Access Handling in PCI-X35

Split Transactions More Efficient Than Delayed36

Example：Requester and Completer on Same Bus37

Example：Requester and Completer on Different Buses38

Dynamic Traffic Analysis and Load Tuning40

Data Phase Parity Error Recovery41

General41

Recovery Usually Not Possible in PCI41

PCI-X Chipset Does Not Monitor PERR42

What the PCI-X Spec Says42

Requester Hardware Doesn′t Handle Error Itself42

With Appropriate Master and Device Driver Design，Recovery Possible42

Device Driver With No Recovery Capability=SERR43

If Bus in PCI Mode，Bridge Monitors PERR43

64-Bit Connection Indication44

MSI Feature Mandatory44

Power Management Mandatory for Add-In Devices44

Snoops Can Be Eliminated44

Memory BARS Must Be 64-Bit Width45

Bus Masters That Access Memory Must Support DAC Command45

Stepping Eliminated45

Fast Back-to-Back Transactions Eliminated46

Chapter 3：Lowest Common Denominator Defines Mode48

Bus Protocol/Speed=Lowest Common Denominator48

Discovering a PCI-X Bus48

Discovering PCI Devices on a PCI-X Bus49

Some Example Systems49

System With No Connectors on PCI-X Bus49

Single Bus System With Connectors49

Systems Supporting Both PCI-X and PCI Environments52

Introduction52

System With Single Host/PCIX Bridge52

Dual Host/PCIX Bridge System54

Chapter 4：Device Types and Bus Initialization56

All Devices Support 33MHz PCI56

General56

133MHz PCI-X Device Must Support 33MHz and 66MHz PCI56

When M66EN Is Grounded on a Card56

Effect of Grounded M66EN on a PCI Source Bridge56

Effect of Grounded M66EN on a PCI-X Source Bridge56

M66EN Usage on a 66MHz PCI Card or a PCI-X Card57

All PCI-X Devices Support 66MHz PCI-X Mode57

PCIXCAP Indicates Protocol/Frequency Required58

General58

PCIXCAP Indicates Capabilities of Card′s First Device61

Device Not Permitted to Use PCIXCAP as Input or Output61

Bridge′s Interpretation of M66EN and PCIXCAP61

Maximum Reliable Speed Verified by Design and Testing63

Supplying PCI-X Devices With Protocol and Speed64

General64

Host/PCIX Bridge Pattern Delivery Sequence64

PCIX-to-PCIX Bridge Pattern Delivery Sequence65

The Sequence65

But First65

Why Bus Must Be Idle When Init Pattern Driven67

Upon Receipt of Pattern，Device Initializes Itself67

Init Pattern Setup and Hold Time67

General67

Relationship With Trhff68

Reassertion of RST# Necessitates Redelivery of Pattern68

General68

Secondary Bus RST# Follows RST# on Primary Side68

Secondary Bus RST# Under Software Control69

Bridge Must Support Interfaces in Different Modes70

Hot-Plug PCI-X Bus Initialization71

Some Systems Permit Hot-Plug of PCI-X Cards71

For Background on PCI Hot-Plug71

Problems Associated With PCI-X Hot-Plug71

Determination of Card Capabilities72

General72

Determining the Presence of a PCI Card73

Unacceptable Method73

Acceptable Method73

Determining the Presence of a 66MHz PCI Card74

Determining the Presence of a 66MHz-Capable PCI-X Card74

Determining the Presence of a 133MHz-Capable PCI-X Card75

Hot-Install of Card With PCIX-to-PCIX Bridge on It75

Description75

How to Avoid Bus Renumbering During Run-Time76

Hot-Install of Card With PCI-to-PCI Bridge on It77

Checking PCIXCAP Without Power Applied to Card78

Changing Secondary Bus Number Configuration Register78

Conservation of Address Space78

General78

Requesting Memory Space79

Requesting IO Space80

Early Configuration Access to Newly-Installed Device80

Possible Adjustment of Max Memory Read Byte Count Values80

Placing Device in Low-Power Mode Requires Quiesce81

Chapter 5：PCI-X Is a Registered Bus83

PCI-X Is a Low-Voltage Swing(LVS)Bus83

Introduction to the Registered Nature of the Bus84

Address/Command Decode Example85

Data Read Example86

Chapter 6：Intro to Commands89

Commands Fall Into Three Categories89

Command Encoding90

Dword Commands92

General92

IO Read and Write Commands92

Memory Read Dword Command92

Configuration Read and Write Commands93

Interrupt Acknowledge Command93

Special Cycle Command95

Burst Commands95

All Burst-Oriented Commands Are Memory Transfers95

Start Address Is Byte-Aligned95

Transfer Length95

Linear Addressing Is Implied96

Memory Read Block Command96

Alias To Memory Read Block Command96

Memory Write Block Command97

Alias To Memory Write Block Command97

Memory Write Command97

Split Completion Command97

Dual-Address Cycle(DAC)Command98

Chapter 7：Intro to Transaction Phases100

The PCI Transaction Phases100

The PCI-X Transaction Phases100

Address Phase100

Attribute Phase100

Response Phase101

Data Phase(s)101

Chapter 8：Intro to Transaction Termination103

Introduction103

Initiator Termination of Transaction104

Byte Count Satisfaction104

Initiator Approaching Buffer Full or Dry Condition104

Connection Timeout105

Early Target Termination of Transaction106

General106

Target Abort107

Reasons for a Target Abort107

Target Abort Always Ends a Transaction107

Retry107

Reasons for Issuing a Retry107

Initiator′s Response to a Retry108

Response to a Retry in PCI108

Response to a Retry in PCI-X108

Detailed Description of Retry108

Single Data Phase Disconnect108

DiSconnect At Next ADB109

Split Response109

Definition109

Commands That Will Not Receive a Split Response110

Bridge Handling of Memory Writes110

Bridge Handling of Transactions Other Than Memory Writes110

Addressing a Location Within the Bridge111

Addressing a Location on the Opposite Side of Bridge111

Chapter 9：Intro to Split and Immediate Transactions114

Definition of Requester and Completer114

Definition of a Sequence114

Definition of Requester ID，Tag，and Sequence ID114

How Does a Device Know Its Requester ID?114

Immediate Transaction116

Definition of an Immediate Transaction116

Immediate Completion Completes the Sequence116

…Unless It′s a Memory Write or Memory Write Block116

…Or Unless First Data Phase of Memory Write Receives Retry117

Memory Writes Are Posted117

General117

Can Be Initiated Before All Write Data Is Ready117

Split Transactions118

What Problem Do Split Transactions Solve?118

Split Completion Uses Sequence ID as the Address118

Requester and Completer May Reside on the Same Bus119

Example119

Split Completion May Contain a Message119

Memory Read May Result in Multiple Split Completion Transactions120

Completer Has All Data Buffered Up：One Split Completion120

Some Data Buffered Up：Multiple Split Completions120

Requester and Completer May Reside on Different Buses121

Example121

Case One：Completer Issues a Split Response122

Case Two：Completer Transfers Data Immediately122

Requester Buffer Space Management124

Allocate Buffer to Hold All of the Data，Then Arbitrate124

On Split Response，Requester Must Commit Buffer Space125

On Immediate Response，Requester Can Release Buffer Space125

Bridge Can Retry or Disconnect Split Completion125

Requesters Must Implement a Split Request Timeout125

Part 2：Transaction Protocol129

Chapter 10：Bus Arbitration129

Stepping Not Permitted129

Request and Grant Signals Are Registered129

Example Arbitration130

Device Design Rules133

No Fast Back-to-Back133

REQ# Can Be Asserted or Deasserted at Any Time134

Issuig REQ# and Then Changing Your Mind134

After REQ# Is Asserted，Assert FRAME# or Deassert REQ134

Initiator Can Start Transaction Two Clocks After GNT# Is Asserted134

GNT# Removal in Clock Prior to FRAME# Too Late to Stop Initiation135

Single Idle Clock Between Transactions135

Multiple Idle Clocks Between Transactions137

Back-to-Back Transactions by Same Initiator138

Device Containing Multiple Initiators138

Arbiter Design Rules138

No GNT# Asserted and REQ# Detected138

Must Allow opportunity to Start Configuration Transaction139

When Bus Not Idle，GNT# Can Be Deasserted Sooner140

If Transaction Not Started，Arbiter May Ignore Master140

Removing GNT# From One Initiator and Giving It to Another141

Parking Recommendation141

Bus Parking141

Floating Bus Causes Power Drain141

Bus Parking Prevents Bus Float141

Rules Associated with Bus Parking142

HOW the Initiator Deals With Preemption143

The Basics143

After Timeslice Exhaustion and Preemption，How Soon Must It Yield?144

What Is the Recommended LT Value?144

How Much Data Can Be Transferred During Default Timeslice?144

Chapter 11：Detailed Command Description147

Dword Commands147

General147

Command Encoding148

Illegal to Assert REQ64# in Dword Transactions148

IO Read and Write Commands149

Basic Description149

Start Address and Byte Enable Format149

Start Address Is Byte-Aligned149

Byte Enable Usage149

IO Transaction With No Byte Enables Asserted149

Target Response to an IO Access151

General151

Completer Handling of an IO Access151

When Bridge Acts as Target of IO Access151

Memory Read Dword Command152

Start Address and Byte Enable Format152

Start Address Is Byte-Aligned152

Byte Enable Usage152

Transaction With No Byte Enables Asserted152

Target Response to a Memory Read Dword Access152

General152

Completer Handling of a Memory Read Dword Access152

Bridge Acts as Target of Memory Read Dword Access153

Configuration Read and Write Commands153

Interrupt Acknowledge Command154

General154

Background154

Host/PCLX Bridge Handling of Interrupt Acknowledge155

System Using APIC Bus to Deliver Interrupts To Processors157

Non-Intel System Implementation159

Special Cycle Command159

General159

Basic Description159

Address Phase160

Attribute Phase160

Data Phase160

In PCI-X Special Cycle Transaction，No Wait States Permitted160

No Target Is Permitted to Respond160

Ending the Transaction161

The Message Types162

Devices That May Initiate a Special Cycle Transaction163

Software-Initiated Special Cycle Transactions163

Burst Commands163

All Burst-Oriented Commands Are Memory Transfers163

Burst Command Encoding163

Start Address Is Byte Aligned165

PCI Memory Addressing165

PCI-X Memory Addressing165

Linear Addressing Is Implied166

Transfer Length166

In PCI，Transfer Length Is Unknown166

In PCI-X，Byte Transfer Count Defines End Address167

Memory Read Block Command167

Basic Description167

Can Be Purely Speculative167

Target Response to Memory Read Block Access167

Must Commit Buffer Space Before Initiating169

Alias To Memory Read Block Command169

Memory Write Block Command169

Basic Description169

If Disconnected，Must Resume With Same Sequence ID170

If Requester Cannot Complete Memory Write170

Technically，a Write Can Be Purely Speculative，But171

Target Never Permitted to Split a Memory Write171

Target Response to Memory Write Block Transaction171

Doesn′t Need All of the Write Data Ready Before Initiating172

Emulating the PCI Memory Write and Invalidate Command172

Alias To Memorg Write Block Command174

Memory Write Command174

Basic Description174

Can Be Purely Speculative175

Target Never Permitted to Split a Memory Write175

Target Response to Memory Write Transaction175

Doesn′t Need All of the Write Data Ready Before Initiating175

Split Completion Command176

Basic Description176

At Minimum，Completer Must Handle One Split Transaction176

Can Be Initiated Even If Bus Master Bit Is Off176

Split Transactions Never Associated With Memory Writes177

One or More Split Completions to Fulfill One Request177

Separate Requests May Be Fulfilled out of Order177

The Address Phase178

The Attribute Phase178

Claiming a Split Completion Transaction180

Requester and Completer Are on the Same Bus180

Requester and Completer Are on Different Buses181

Master Abort or Target Abort on a Split Completion182

Treatment of Byte Enables182

Requester Must Accept the Split Completion Data182

When Bridge Is Target of Completion，Can Retry or Disconnect182

Initiator of Split Completion Can Disconnect183

After Disconnect，Pick Up Where You Left Off183

Split Completion Messages183

To Disconnect First Split Completion at Imminent ADB184

Disconnecting First Split Completion Is Problematic184

The Problem184

The Solution185

Bridge Buffer Space Problem Due to Corrupted Split Completion186

Dual-Address Cycle(DAC)Command187

Chapter 12：Latency Rules189

Initiator Latency Rules189

Don′t Start Transfer If You′re Not Ready189

No Initiator Wait States Permitted…Ever190

Behavior When Preempted191

Target Latency Rules191

Target Response Time During Initialization Period191

What′s Going on During Initialization Time?191

Definition of Initialization Period in PCI191

Definition of Initialization Period in PCI-X192

Initialization Period and Hot-Plug192

Target Can Ignore 16-Clock Rule During ROM Shadowing192

Target Response Time Limit During Run-Time192

Response Time Limit When No Data Transferred192

Response Time Limit When Data Transferred193

Host/PCIX Bridge Must Obey 16-Clock Rule193

In PCI193

In PCI-X193

Subsequent Data Phase Target Latency Rule193

Maximum Completion Time193

In PCI193

How PCI-X Is Different194

How Can You Prevent Violation of This Time Limit?195

Chapter 13：The Address，Attribute and Response Phases198

All Transactions Begin With Address and Attribute Phases198

Memory Transaction May Have Two Address Phases199

Attributes Always Delivered on Lower Half of Bus200

Address/Attribute Format Depends on Command Type200

Memory Burst Format200

Description200

No Snoop Attribute Bit201

Background201

Bridge Knows AGP′s Area of Memory Is Non-Cacheable201

Memory Used by PCI Masters May or May Not Be Cached202

Snoops Slow Down PCI Accesses to Main Memory202

Snoop Traffic on Processor Bus Can Hurt Processor(s)202

Main Memory Less Available to Processors202

PCI-X Driver Can Make Requester′s Buffer Uncacheable202

Only Host/PCIX Bridge Pays Attention to NS Bit203

When NS Is Set and CPU Has a Lock in Force203

NS Must Be 0 in Some Transactions203

Dword Command(other than Config)Format205

Memory Read Dword and Io Format205

Special Cycle and Interrupt Acknowledge Format206

Configuration Command Format206

Two Types of Configuration Transactions206

Type 0 Configuration Access207

TYPe 1 Configuration Access207

Type 0 Configuration Access Format207

TYPe 1 Configuration Access Format208

Split Completion Command Format209

The Response Phase：Connecting With the Target210

Chapter 14：Dword Transactions216

General216

General Format of Timing Diagram Descriptions216

IO Read and Memory Read Dword216

Example One216

Example Two220

IO Write224

Example One224

Example Two227

Example Three230

Configuration Read and Write Transactions234

Interrupt Acknowledge Command234

Special Cycle Command235

Chapter 15：Burst Transactions240

Introduction240

Short Transfer Within a Block240

Long Transfer，But Disconnect on First Block Boundary240

General Format of Timing Diagram Descriptions240

Memory Read Block Transaction241

Memory Read Block：Detailed Example241

Memory Read Block：Variation One245

Memory Read Block：Variation Two246

Memory Read Block：Variation Three247

Memory Read Block：Variation Four248

Memory Read Block：Variation Five249

Memory Read Block：Variation Six250

Memory Read Block：Variation Seven251

Memory Read Block：Variation Eight252

Memory Write Block Transaction253

Memory Write Block：Detailed Example253

On Burst Writes，Insert Wait States in Pairs257

Memory Write Transaction260

Memory Write：Detailed Example261

Memory Write：Variation One265

Memory Write：Variation Two266

Memory Write：Variation Three267

Memory Write：Variation Four268

Memory Write：Variation Five269

Memory Write：Variation Six270

Memory Write：Variation Seven271

Memory Write：Variation Eight272

Memory Write：Variation Nine273

Split Completion Transaction274

Split Completion Returning Block of Read Data275

Returning a Split Completion Error Message276

Alias To Memory Block Commands277

Chapter 16：Transaction Terminations279

General Format of Timing Diagram Descriptions279

Termination by the Initiator280

General280

Byte Count Satisfaction280

Introduction280

Ending Transaction of Four or More Data Phases281

Ending Transaction of Less Than Four Data Phases282

Introduction282

Three-Data-Phase Transaction282

Two-Data-Phase Transaction284

One-Data-Phase Transaction286

Initiator Issues Disconnect at Next ADB289

Initiator Termination Due to Connection Timeout290

Termination By the Target290

Target Abort290

Target Abort Is Always Fatal290

Some Reasons Target Issues Target Abort290

Broken Target290

IO Addressing Error290

Address Phase Parity Error290

Initiator′s and Target′s Response to Target Abort290

Example Target Abort Issued in First Data Phase291

Example Target Abort Issued in Subsequent Data Phase293

Target Issues a Retry294

Target Issues Single Data Phase Disconnect297

General297

Special Case Scenario299

Target Issues Disconnect At Next ADB299

Disconnect Issued Four Or More Data Phases From ADB300

Target Issues Disconnect Too Close to Block Boundary301

To Disconnect When Start Address Very Close to ADB302

Start Address Three Data Phases From Block Boundary303

Start Address Two Data Phases From Block Boundary304

Start Address One Data Phase From Block Boundary306

Target Issues a Split Response308

Split Response for a Read308

Split Response for an IO or Configuration Write310

Chapter 17：Split Completion Messages313

Purpose of Split Completion Messages313

SCM Always Terminates a Sequence315

Upon Receipt of Error Message，Set Status Bit315

Message Format316

Address Phase Format316

Attribute Phase Format316

Data Phase Message Format317

Write Completion Indication322

Good Completion of Split IO or Configuration Write322

Bad Completion of a Split IO or Configuration Write323

Read Completion Indication323

Good Completion of a Split Dword Read323

Good Completion of a Split Burst Memory Read323

Bad Completion of a Split Dword Read324

Bad Completion of a Split Burst Memory Read324

General324

Remaining Byte Count and Remaining Lower Address Fields324

Device-Specific Error Handling325

Chapter 18：64-Bit Transactions327

General Format of Timing Diagram Descriptions327

64-Bit Data Transfers and 64-Bit Addressing：Separate Capabilities328

64-Bit Extension Signals328

REQ64# and ACK64# Have Same Timing as FRAME# and DEVSEL329

In Attribute Phase，Upper Bus Reserved and Driven High330

Block Length Remains the Same330

Bursts Cannot Cross 264 Boundary330

REQ64# Not Permitted in Dword Transactions330

General330

…Unless It′s a Split Completion331

MSI Write Always Writes a Single 32-Bit Data Value331

Bridge Must Support DAC on Both Interfaces331

Width of Function′s Connection to Bus332

General332

Add-In Card With a Bridge334

Determining the Width of a Bridge′s Interfaces334

64-Bit Cards in 32-Bit Add-In Connectors335

Pullups Prevent 64-Bit Extension From Floating When Not in Use336

Problem：A 64-Bit Card in a 32-Bit PCI Connector336

How 64-Bit Card Determines Type of Slot Its Installed In338

64-Bit Data Transfer Capability339

64-Bit Transfers：Only Burst Memory Operations340

Start Address Byte-Aligned340

64-Bit Target′s Interpretation of Address341

32-Bit Target′s Interpretation of Address341

64-Bit Memory Read Block With 64-Bit Target341

64-Bit Write Block or Split Completion With 64-Bit Target347

64-Bit Memory Write With 64-Bit Target352

Start Address Alignment Defines Data Path Usage354

Introduction354

64-Bit to 64-Bit Connection354

64-Bit to 32-Bit Connection354

64-Bit Memory Reads From 32-Bit Targets359

Starting on Even Dword359

Starting on Odd Dword365

64-bit Memory Writes to 32-Bit Targets366

Starting on Even Dword366

Starting on Odd Dword368

Example One368

EXample Two369

Example Three370

Example Four371

Example Five372

Addressing Memory Above 4GB Boundary372

Introduction372

Introduction to the DAC Command373

DAC Support Mandatory for All Initiators373

Memory Targets Must Support Wide BARs and DAC374

Use of DAC Command Changes DEVSEL# and Master Abort Timing375

Example 32-Bit Transaction Using DAC Command375

Example 64-Bit Transaction Using DAC Command377

DEVSEL# Must Not Be Asserted Too Soon378

Add-In Card Trace Length379

Parity Generation and Checking382

Chapter 19：Parity Generation and Checking383

General Discussion of Parity Generation383

Parity Generation Is Mandatory383

In Data Phases of Writes and Split Completions384

Initiator Must Generate Correct Data Phase Parity384

Toggle Data and Parity When Target Inserts Wait State Pairs384

In Reads，the Target Sources Data and Parity384

First Data Phase Data and Parity Can Be Delayed384

Subsequent Data Phase Data and Parity Never Delayed384

General Discussion of Parity Checking384

Checking Required in Address and Attribute Phases384

Parity Checking Is Generally Required In Data Phases385

Target Data Parity Checking During Write or Split Completion385

Initiator Parity Checking During Reads385

Parity Not Checked During First Data Phase Wait States385

Parity Checked one Clock After Each Subsequent Data Phase385

In Any Phase，Agent Driving AD Bus Supplies Parity385

As in PCI，Even Parity Is Used386

No Parity in Response Phase386

Address Phase Parity387

Address Phase Parity Checking Required387

When DAC Is Used，Check Both Packets387

On Error，SERR# Required387

Error Detected Before Transaction Claimed387

Error Detected After Transaction Claimed388

Parity Error in Split Completion Address Phase388

Attribute Phase Parity389

Means Sequence ID and/or Byte Count Corrupted389

When Attributes Corrupted and Split Response Issued389

Data Phase Parity389

Parity Always Covers Full Width of Data Bus389

Parity Driven One Clock After Information Presented390

Similar to PCI，But Different(due to registered bus)390

Parity-Related Initiator Responsibilities390

Initiator May Be a Requester，a Bridge，or a Completer390

Requester′s Parity-Related Responsibilities During a Write390

Drive Data，Byte Enables and the Parity391

Requester Checks PERR391

Requester Actions When PERR# Asserted by Target391

Requester′s Actions on PERR# and Split Response391

Bridge′s Parity-Related Responsibilities During a Write391

Drive Data，Byte Enables and the Parity392

Bridge Checks PERR392

Bridge Actions When PERR# Asserted by Target392

Initiator′s Parity-Related Responsibilities During a Split Completion394

Who Initiates Split Completion Transactions?394

Initiator Drives Data，Byte Enables and Parity394

Initiator Does Not Monitor PERR394

Initiator′s Parity-Related Responsibilities During a Read395

General395

First Read Data Item and Parity Can Be Delayed by Target395

Subsequent Data Phases of a Read395

Parity Checking by Initiator During a Read395

Split Response Dummy Data Corrupted396

Requester′s Parity-Related Responsibilities During a Read396

Read Error and Data Parity Error Recovery Enable Bit=1397

Read Error and Data Parity Error Recovery Enable Bit=0397

Bridge′s Parity-Related Responsibilities During a Read397

General397

Bridge Handling of Parity Error in Immediate Read397

Parity-Related Target Responsibilities398

Target May Be a Completer，a Requester，or a Bridge398

Target′s Responsibilities During a Write398

When Completer Acts as the Target of the Write399

When a Bridge Acts as the Target of the Write399

Target′s Responsibilities During a Split Completion399

When Requester Acts as the Target of a Split Completion399

When a Bridge Acts as the Target of a Split Completion400

Target′s Responsibilities During a Read400

Data Parity Generation/Checking in PCI-X401

General Format of Timing Diagram Descriptions401

Parity in Memory Write Block(or Alias)or Split Completion401

Parity in a Memory Write Transaction406

Parity in Memory Read Block(or Alias)Transaction406

Parity in Memory Read Dword or IO Read Transaction411

Parity in Configuration Read415

Parity in IO Write Transaction416

Parity in Configuration Write420

Part3：Device Configuration425

Chapter 20：Configuration Transactions425

Configuration Software Mechanism Same as PCI425

Configuration Transactions Can Only Flow Downstream426

Special Cycle Request Can Flow Upstream or Downstream426

Type 0：Access Registers in Function on This Bus426

Device Selection426

Bus/Device Auto-Updated by Each Type 0 Config Write430

General430

Host/PCIX Bridge Device Number Assignment430

Type 1：Access Registers in Function on Bus Farther out in Hierarchy430

General Description430

Some Example Scenarios433

Example One433

Example Two433

Example Three433

Example Four434

Type 0 Configuration Transactions435

Action Taken on Master Abort435

IDSELs Routed Over Upper AD Lines436

IDSEL Output Pins/Traces Allowed on Host/PCIX Bridge437

Description437

Type 0 Access by a Tool438

Resistive Coupling Requires Address Pre-Drive438

Bridge With IDSEL Pins Also Requires Address Pre-Drive439

Type 0 Configuration Read439

Type 0 Configuration Write443

Type 1 Configuration Transactions447

Although Not Necessary，Address Pre-Drive Used447

Type 1 Configuration Access Address Format447

Target Bus′s Source Bridge Converts Type 1 to Type 0 Access448

Type 1 Transaction Examples448

Arbiter′s Treatment of Configuration Access449

Generation of Special Cycle Under Software Control450

General450

PCIX-to-PCIX Bridges Pass Special Cycle Request to Target Bus451

Special Cycle by Device Other Than Host/PCIX Bridge452

Chapter 21：Non-Bridge Configuration Registers453

Detecting a PCI-X Capable Bridge453

Detecting Presence of PCI-X Capable Bridge/Bus453

Detecting Width of Bridge′s Interfaces457

Detecting Frequency Support of Bridge′s Interfaces458

Frequency Support of Bridge′s Primary Interface458

Frequency Support on Bridge′s Secondary Interface458

Checking Current Frequency/Protocol of Secondary Bus459

Detecting Capabilities of Functions on Bus459

Format of Non-Bridge Function′s PCI-X Capability Registers459

Detecting PCI Functions461

Detecting Width of PCI-X Functions461

Detecting Frequency Support of PCI-X Functions462

Most PCI Configuration Registers Remain Unchanged462

Some PCI Config Registers Affected by Protocol Mode463

Some Register Default Values Affected463

Implementation of Some Registers Affected463

Usage of Some Registers Affected464

Base Address Registers(BARs)464

Memory Base Address Registers464

PCI and Memory BARs464

Must Be Implemented as 64-bit Decoders464

Definition of Prefetchable Memory464

Minimum Memory Range465

Diminishes Overall Number of BARs465

IO Base Address Registers467

Command Register Bits Affected by Protocol Mode467

Introduction467

Fast Back-to-Back Enable Bit468

Stepping Control Bit468

Memory Write and Invalidate Bit468

Bus Master Bit468

Status Register Bits Affected by Protocol Mode469

Latency Timer Default Affected by Protocol Mode469

Cache Line Size Configuration Register470

Capabilities Pointer Register470

Function′s PCI-X Capability Register Set470

Register Set Format470

Background on Load Tuning471

Adjusting Requester′s Split Transaction Queue Size471

Problem471

Solution471

Adjusting Requester′s Memory Read Transaction Size471

Problem471

Solution472

PCI-X Command Register472

Max Outstanding Split Transaction Field473

Max Memory Read Byte Count Field474

Enable Relaxed Ordering474

RO Command Bit Enables/Disables Use of RO Attribute Bit474

General Description475

Usage in Memory Read475

Usage in Memory Write475

After Disconnect，Be Consistent476

Restrictions on Use476

For Additional Information476

Data Parity Error Recover Enable476

PCI-X Status Register476

Bus，Device and Function Number Fields477

Why They Are Necessary477

Function Number Is Hardwired477

Bus/Device Auto-Updated by Type 0 Configuration Write477

Note for PCI-X Tool Designer478

64-Bit Device Status Bit479

133MHz-Capable Status Bit479

Split Completion Discarded(this is not a good thing!)480

Unexpected Split Completion(this is also not a good thing!)480

Device Complexity481

General481

What Use Is This Bit?481

Definition of a Simple Device481

Rules Governing Behavior of a Simple Device481

Designed Max Memory Read Byte Count484

Designed Max Outstanding Split Transactions484

Designed Max Cumulative Read Size484

Chapter 22：Bridge Configuration Registers487

Discovering a PCIX-to-PCIX Bridge487

Many Bridge PCI Configuration Registers Unchanged487

Some Bridge PCI Configuration Registers Affected by Mode488

Command Register Affected490

Status Register Affected490

Capability Pointer Register Affected490

Secondary Status Register Affected490

General490

Fast Back-to-Back Capable Bit Affected491

Master Data Parity Error/Detected Parity Error Bits Affected491

DEVSEL# Timing Bit Field491

Cache Line Size Register Affected491

Both Latency Timer Registers Affected492

Base Address Registers(BARs)Affected492

Secondary Bus Number Register Affected493

In PCI Mode，No Change493

In PCI-X Mode，Secondary Requesters May Have Pending Split Accesses493

Hot-Plug Event May Cause Bus Renumbering494

RST# Causes Functions to Forget Bus/Device Numbers494

Prefetchable Base/Limit Registers Affected495

Prefetchable Base/Limit Extension Registers Affected495

Bridge Control Register Affected496

Bridge′s PCI-X Capability Register Set497

PCI-X Capability Register Set Format497

PCI-X Secondary Status Register498

64-Bit Device Status Bit499

133MHz Capable Status Bit499

Split Completion Discarded Bit499

Unexpected Split Completion Bit500

PCI Master Addresses PCI-X Target on Secondary500

Problem：Bridge′s Requester ID，but Bad Tag500

Error Handling500

Bridge Secondary Interface Efficiency Status Bits501

Background on Efficiency Status Bits501

Split Completion Overrun Bit501

Split Request Delayed Bit502

Secondary Clock Frequency Bit Field502

PCI-X Bridge(Primary Interface)Status Register503

64-Bit Device Status Bit503

133MHz Capable Status Bit503

Split Completion Discarded Bit504

Unexpected Split Completion Bit504

PCI Master Addresses PCI-X Target on Primary504

Problem：Bridge′s Requester ID，but Bad Tag505

Error Handling505

Bridge Primary Interface Efficiency Status Bits505

Background on Efficiency Bits505

Split Completion Overrun Bit505

Split Request Delayed Bit506

Bus/Device/Function Number Fields506

Split Transaction Control Registers506

Basic Register Format506

The Bridge′s Split Completion Data Buffers507

Controlling Bridge′s Use of Its Split Completion Data Buffers507

Capacity Value Indicates Size of Respective Data Buffer507

Limit Value Controls Bridge′s Perception of Buffer Size508

Allocation Mode508

Virtual Buffer Space Mode509

Flood Mode509

Regaining Control After Operating in Flood Mode509

For More Information on Load Tuning511

Optional Bridge Registers511

Part4：Load Tuning515

Chapter 23：Load Tuning Mechanisms515

Introduction to Load Tuning515

Non-Bridge Function Tuning516

Information Fields516

Adjustable Fields/Registers516

Bridge Tuning519

Adjusting Usage of Split Completion Buffers519

Introduction519

Interpreting the Efficiency Bits519

Additional Spec Comments519

Adjusting Bridge′s Timeslice Values524

Bridge Is Surrogate for Initiators on Both Sides of Bridge524

Software Must Assign Bridge Two Timeslices525

Load-Tuning Software Can Choose Timeslice Other Than 64d525

Part 5：PCI-X Bridges532

Chapter 24：PCIX-to-PCIX Bridges532

Performs Same Function as a PCI-to-PCI Bridge532

Support for DAC Command532

Downstream Movement of DAC optional for PCI Bridge532

PCI-X Bridge Must Support Downstream DAC Movement533

Bus Width534

Memory Writes Crossing Bridge Are Always Posted534

Other Transactions Crossing Bridge Are Always Split534

How the Bridge Claims Split Completions534

When Bridge Can Use Retry or Disconnect At Next ADB535

When Bridge Can Issue a Retry535

When Bridge Can Issue a Disconnect At Next ADB536

Interfaces Can Be in Different Modes/Speeds536

Translating PCI to PCI-X536

General536

Writes Are Posted537

All Others Treated as PCI Delayed Transaction537

On PCI Side，Bridge Follows PCI Ordering Rules538

Translating the Transaction Type538

Creating the Attributes541

Attribute Bits541

Requester ID542

Transaction Tag542

Byte Transfer Count542

Target May Treat as Immediate or as Split Transaction543

Translating PCI-X to PCI543

General543

Writes Are Posted544

All Others Treated as Split Transactions544

Translating the Transaction Type544

PCI Target May Treat as Immediate or Delayed Transaction547

Bridge Creation of a Split Completion548

Effect of Relaxed Ordering Attribute Bit549

Error Handling549

Bridge Error Class SCMs549

Error Handling Defined by Mode of Originating Interface549

Error Handling When the Originating Bus Is in PCI-X Mode550

Scenario 1：Data Parity Error in Immediate Read on Destination Bus550

Scenario 2：Data Parity Error on Split Write551

General551

Scenario 2a551

Scenario 2b552

Scenario 2c553

Scenario 2d554

Scenario 3：Data Parity Error on Split Completion555

Originating Bus Parity Error on Split Completion Read Data555

Originating Bus Parity Error on SCM555

Destination Bus Parity Error on Data or SCM556

Bridge Forwards SCMs Quietly(without getting involved)556

Scenario 4：Data Parity Error on Posted Memory Write556

Scenario 5：Master Abort on Destination Bus557

General557

Master Abort When Forwarding Split Request557

Master Abort on Posted Memory Write558

Master Abort on Split Completion559

Scenario 6：Target Abort on Destination Bus559

Bridge Signals Target Abort559

Bridge Receives A Target Abort on Split Transaction559

Bridge Receives Target Abort on Memory Write560

Bridge Receives Target Abort on Split Completion560

Error Handling When Originating Bus in PCI Mode560

Background560

Bridge Handles Errors Same as PCI Bridge Unless SCM Error561

SCM Error on a Split Read561

SCM on Split Write561

Corrupted Split Completion562

Buffer Size562

Posted Memory Write Buffer Size562

Split Completion Data Buffer Size563

Buffer Space for Memory Read Data564

General564

The Problem564

When Limit=Capacity，This Is Not a Problem564

When a Request Is Bigger Than the Bridge Buffer564

Application Bridge564

Bridge Acceptance Rules567

Ordering and Passing Rules568

Same Rules as PCI Except569

Relaxed Ordering Effect on Transaction Ordering569

Relaxed Ordering Effects on Memory Reads569

Relaxed Ordering Effects on Memory Writes570

Split Transaction Effects on Transaction Ordering571

General571

Same Sequence Split Completions Must Remain in Order571

Relaxed Ordering Can Affect Split Completion Delivery572

The Rules572

Decomposing Split Transactions(sounds morbid!)577

Chapter 25：Locked Transaction Series579

Definition of Downstream and Upstream579

Basics580

Only Host/PCIX Bridge Originates Downstream Locked Series581

PCI-X Bridges only Pass Locked Series Downstream581

Only EISA Bridge Originates Upstream Locked Traffic582

Application Bridge May or May Not Support Locking582

EISA Bridge Supports LOCK# As Input，Not as Output583

Non-Bridge Devices Ignore LOCK583

Sequence of Events583

Split Completion Error Message Terminates Lock586

Upstream Bridge(Initiating Bridge)Rules587

Downstream Bridge(Target Bridge)Rules587

Arbitration588

Starting Locked Transaction Series588

Retry/Target Abort/Master Abort Cancels Lock588

First Access of Series Receives Retry588

General588

If Target Is a PCI-to-PCI Bridge588

If the Target Is a PCIX-to-PCIX Bridge589

First Access of Series Receives Target or Master Abort589

First Transaction Has Immediate Completion589

First Transaction Receives Split Response592

Continuing Locked Transaction Series595

Attempted Access to Bridge by Device Other Than Owner597

Last Transaction in Locked Series598

If Last Transaction Receives Immediate Completion598

If Last Transaction Receives Split Response599

The Unlocking of a Target Bridge599

When Bridge Starts Second Series Immediately After First599

Retry Issued to Owner Not a Problem599

DAC Command Lock Timing600

In the First Access600

In Subsequent Accesses of Locked Series600

Part 6：Error Detection and Handling603

Chapter 26：Error Detection and Handling603

Handling of a Target Abort603

Introduction603

Requester Receives Target Abort604

Completer Receives Target Abort on Split Completion606

When Split Completion Target Abort Is Permissible606

Discard of Completion for a Write or Non-Prefetchable Read607

Discard of Completion for IO，Config，or Prefetchable Memory Read608

Handling of a Master Abort609

Introduction609

Requester Handling of Master Abort609

If Host/PCI Bridge Type 0 Config Transaction609

If Not Host/PCIX Bridge Type 0 Config Transaction610

If Requester Capable of Generating Interrupts610

If Requester Can′t Generate Interrupts610

Completer Handling of Master Abort on a Split Completion610

General610

Discard of Completion for a Write or Non-Prefetchable Read611

Discard of Completion of IO，Config，or Prefetchable Memory Read611

Target Handling of Address or Attribute Phase Parity Error612

Data Phase Parity612

PCI Chipset Typically Murders System on Data Parity Error612

In PCI-X，Chipset Doesn′t Monitor PERR613

General613

Requester′s Data Parity Error Recovery Enable Bit613

Basic Description613

Set by OS or Driver′s Initialization Code at Startup Time614

If Not Set，PCI Compatibility Dictates Murdering System614

Recovery Must Be Performed Under Software Guidance615

Driver Reports Error to OS615

OS Instructs Driver on Action(s)to Take615

OS Vendor Specifies Who Clears Parity Error Status Bits615

Requester Handling of PERR# With Split Response616

Data Error Received With Split Response on Read616

Data Error Received With Split Response on Dword Write618

Requester/Completer Handling of Data Error During SPlit Completion620

Split Read Errors620

General620

Read Data Returned in One or More Split Completions621

Internal Completer Error Can Occur at Any Time622

Receipt of SCM Terminates Read Sequence622

Effect of SCM on a Bridge623

Effect of SCM on the Requester623

Requester Handling of Unexpected Split Completion626

Requester Handling of Split Completion Error Messages627

Handling Completer Byte Count Out-of-Range Error627

Memory Writes Never Split，so SCMs Don′t Apply627

Read Immediate Treated Same as Write at Device Boundary627

Split Read Straddling Device Boundary Causes SCM627

Read Burst Straddling Device Boundary Considered Rare Case628

Handling Completer Split Write Data Parity Error629

Handling Completer Device-Specific Error629

Handling Master Abort on Other Side of a Bridge629

Error Description629

Effect of Master Abort on Bridge630

Bridge Interrupt Acknowledge Master Aborts630

Bridge Special Cycle Master Aborts630

Bridge IO Read Master Aborts630

Bridge IO Write Master Aborts632

Bridge Configuration Read Master Aborts632

Bridge Configuration Write Master Aborts632

Bridge Memory Read Dword Master Aborts632

Bridge Memory Write Master Aborts632

Bridge Memory Read Ends in Master Abort633

Bridge Split Completion Ends in Master Abort633

Effect of Master Abort SCM on Requester635

Requester Interrupt Acknowledge Gets Master Abort SCM635

Requester Special Cycle Gets Master Abort SCM635

Requester IO Read or IO Write Gets Master Abort SCM636

Requester Configuration Read Gets Master Abort SCM636

Requester Configuration Write Gets Master Abort SCM636

Requester Memory Read Dword Gets Master Abort SCM637

Requester Memory Write Gets Master Abort SCM637

Requester Memory Read Gets Master Abort SCM637

Requester Split Completion Gets Master Abort SCM638

Handling Target Abort on Other Side of Bridge638

Error Description638

Effect of Target Abort on Bridge638

Bridge Interrupt Acknowledge Target Aborts639

Bridge Special Cycle Target Aborts639

Bridge IO Read Target Aborts639

Bridge IO Write Target Aborts640

Bridge Configuration Read Target Aborts640

Bridge Configuration Write Target Aborts640

Bridge Memory Read Dword Target Aborts640

Bridge Memory Write Target Aborts640

Bridge Memory Read Block Ends in Target Abort641

Bridge Split Completion Ends in Target Abort641

Effect of Target Abort SCM on Requester642

Requester Interrupt Acknowledge Gets Target Abort SCM642

Requester Special Cycle Gets Target Abort SCM642

Requester IO Read or IO Write Gets Target Abort SCM642

Requester Configuration Read Gets Target Abort SCM643

Requester Configuration Write Gets Target Abort SCM643

Requester Memory Read Dword Gets Target Abort SCM643

Requester Memory Write Gets Target Abort SCM644

Requester Memory Read Gets Target Abort SCM644

Requester Split Completion Gets Target Abort SCM644

Handling Split Write Data Parity Error on Other Side of Bridge644

Error Description644

Bridge May Deliberately Forward a Bad Split Write644

…Or Split Write May Become Corrupted When Bridge Forwards It645

Effect of Split Write Data Parity Error on Bridge645

Effect of Split Write Data Parity Error on Requester645

Usage of SERR646

Part 7： Electrical Issues651

Chapter 27：Electrical Issues651

Introduction651

LVS Bus651

Attention to Detail651

Most Parameters Tighter Than PCI652

Maximum Number of Loads and Connectors on Bus652

Cards Keyed as 3.3 Volt or Universal Cards652

133MHz PCI-X Device Must Support 66MHz PCI652

Add-In Card Trace Lengths652

Initialization Pattern Setup/Hold Time653

General653

Trhff Must Be Taken Into Account653

IDSEL Routing654

General654

IDSEL Series Resistor Value655

Appendix A：Protocol Rules659

Introduction659

General Bus Rules659

Initiator Rules661

Target Rules662

Bus Arbitration Rules663

Configuration Transaction Rules664

Parity Error Rules665

Bus Width Rules665

Split Transaction Rules666

Appendix B：Glossary671

Index683